A NOR or NAND flash EEPROM memory cell, as well as many other types of memory cells known in the art, may be written a limited number of times during the cell lifetime. While the number of write cycles is dependent on the memory cell technology, after an address reaches its specified write cycle limit, it may no longer operate according to designed specifications.
Wear leveling techniques have been employed by memory devices to reduce disparities in the write cycles, but such techniques are typically confined to level the wear of a memory cell or group of cells within a subdomain of the memory device. For example, in some flash memory devices wear leveling is performed at a block level of granularity within a physical partition of the memory device to level write cycles across the blocks within the single physical partition. In such block level methods, wear leveling is performed independently within each partition of the memory device.
While wear leveling within a given partition may be conveniently implemented by swapping two blocks within the partition containing a target block being erased by a user or host of the memory device, a disparity in write cycles between blocks in separate partitions may still occur and reduce the lifetime of the memory device. Furthermore, read while write (RWW) restrictions generally preclude direct application of block wear leveling algorithms to wear level across partitions because a background copy of a block from one partition of a memory device to a different partition could conflict with a user read request.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.